- Teledyne (Milpitas, CA)
- …+ ** RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/SystemVerilog) for high-speed protocol, packet parsing, timestamping, and ... We are looking for a top-notch Staff Logic Design engineer who has the right composition of knowledge, experience,...for FPGA or ASIC. + Strong proficiency in **Verilog/SystemVerilog RTL design** . + Experience with one or more… more
Locations:
California