- Altera (San Jose, CA)
- A leading technology company in San Jose, California, is seeking a Timing Engineer to lead timing activities for subsystems. This role requires extensive ... experience in timing analysis and sign-off, as well as proficiency with...proficiency with scripting languages. The ideal candidate will drive timing closure and collaborate closely with design teams. A… more
- Altera (San Jose, CA)
- Altera . Timing Engineer / Lead page is loaded## Timing Engineer /Leadlocations: San Jose, California, United Statestime type: Full timeposted on: Posted ... #1 FPGA company!**About the Role**Altera is looking for a Timing Engineer to lead ...working/collaborating with the design and architecture team.**Key Responsibilities: Drive timing closure at block level and sub-system… more
- Harris Geospatial Solutions (San Diego, CA)
- …air, land, sea and cyber domains in the interest of national security. Job Title: Lead , Firmware (FPGA) Engineer Job Code: 30614 Job Location: San Diego, CA Job ... Friday off!) Job Description: As a Senior Specialist FPGA Engineer , you will play a critical role in the...digital design for RF and FPGA development, you will lead complex projects, guiding the design process from initial… more
- Altera (San Jose, CA)
- …to becoming the world's #1 FPGA company!**About the Role**As a Sr. Physical Design Tech Lead / Engineer at Altera, you will play a critical role in our backend ... performance/power/area (PPA) goals, with particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA… more
- Analog Devices, Inc. (Wilmington, MA)
- …Digital Design Engineer ** **About the Role** As a Senior Digital Design Engineer , you will lead block -level designs and verification efforts. You'll ... Digital IC Design Engineer page is loaded## Digital IC Design Engineerlocations:...team to ensure a successful project development. **Key Responsibilities Lead block -level digital designs and verification activities*… more
- Credo Semiconductor, Inc. (San Jose, CA)
- …PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities Lead and drive top-level, IP, and block -level physical implementation ... Connect. About the Role As a Senior Physical Design Engineer , you will manage all aspects of physical design...from RTL to GDSII. Focus on timing , power, and area (PPA) optimization for high-speed SerDes… more
- Apple Inc. (Santa Clara, CA)
- …Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block -level physical design. Description As a CPU Physical Design Engineer ... and place-and-route tools targeting ambitious PPA goals Will be responsible for block -level physical design delivery along with closure of backend flows, electrical… more
- Encore Semi Llc (San Jose, CA)
- …US citizen or Lawful Permanent Resident. Remote (Anywhere in US) Responsibilities Lead full-chip and block -level physical design for advanced semiconductor ... Sr Physical Design Engineer (Remote) Full-time: Salary + Benefits + Bonuses...clock architectures, placement and routing, and chip assembly. Own timing closure, signal integrity, power, noise, yield, and physical… more
- DRW Holdings, LLC. (Chicago, IL)
- …This person will participate in the full development lifecycle, including system and block level testing, of low latency high throughput FPGA design. This role is ... implement new FPGA applications (synthesis, place & route, static timing analysis, documentation) from the ground up Research and...FPGA Highly autonomous with a can-do attitude able to lead an FPGA based project from system requirements to… more
- L3Harris (San Diego, CA)
- …air, land, sea and cyber domains in the interest of national security. Job Title: Lead , Firmware (FPGA) Engineer Job Code: 30614 Job Location: San Diego, CA Job ... Friday off!) Job Description: As a Senior Specialist FPGA Engineer , you will play a critical role in the...digital design for RF and FPGA development, you will lead complex projects, guiding the design process from initial… more
- Broadcom (Fort Collins, CO)
- …and packaging teams to balance performance, power, and area (PPA) targets. + Lead top-level timing closure, congestion analysis, and ECO implementation to ensure ... support to internal and external partners. + Apply a deep understanding of block PnR, timing closure, physical verification, and IR/EM analysis to achieve… more
- L3Harris (Fort Wayne, IN)
- …the interest of national security. Job Title: Senior Specialist, FPGA Digital Design Engineer Job Code: 32307 Job Location: Fort Wayne, IN Job Schedule: 9/80 (Every ... and airborne domains with defense, intelligence, and commercial applications. As an FPGA design engineer , you will be directly involved in one or more of the areas… more
- Amazon (Sunnyvale, CA)
- …using test benches constructed using UVM, System C and DPI-C. . Ensure that the block meets DFT, timing and power targets by working closely with the ... work at Amazon! We're hiring a Sr. RTL Design Engineer - Wireless Modem within a high performance ASIC...system specification to chip specification to RTL to optimizing timing / power to chip level validation. . Develop… more
- ADM (Oak Brook, IL)
- **98589BR** **Job Title:** Senior Electrical SIS Instrumentation Engineer - Decatur, IL **Department/Function:** Engineering **Job Description:** **Senior Electrical ... SIS Instrumentation Engineer - Decatur, IL** This is a permanent, full-time,...with respect to system modernization and maintenance, and will lead and support small and large instrumentation and controls… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...the entire line of products. + Be a mentor/technical lead for junior team members. What we need to… more
- Actalent (Dallas, TX)
- …+ Provide technical expertise and leadership on programs, collaborating with the Project Engineer to lead the development team in achieving committed product ... Job Title: RF Mixed Signal Circuit Design Engineer Job Description We are seeking a Sr....and passive filters, and power distribution systems. + Perform block level and transistor level layout design and optimization… more
- RTX Corporation (Marlborough, MA)
- …These systems allow end users to protect people and property. As a Network Engineer you will join our Hardware and Infrastructure Engineering Team as part of our ... providing support to existing fielded systems. We are seeking a network engineer with experience in design and implementation of networking solutions. This… more
- NVIDIA (Santa Clara, CA)
- …next wave of computing. We are now looking for a motivated Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing Circuits ... significant and exciting role in improving the netlist and timing quality of our designs and if you are...all the way to platform level. + Perform detailed block -level and system-level simulations to ensure good reliability, performance,… more
- Leonardo DRS, Inc. (Cypress, CA)
- …system simulation, synthesis, resource and power utilization analysis, place and route, timing analysis, verification, and integration activities + Block level ... applications. We are seeking a Senior Principal Digital Design Engineer to join the company in the development of...to provide and receive constructive criticism + Ability to lead major problem resolution efforts and support regaining or… more
- NVIDIA (Santa Clara, CA)
- …wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing Circuits ... significant and exciting role in improving the netlist and timing quality of our designs and if you are...all the way to platform level. + Perform detailed block -level and system-level simulations to ensure good reliability, performance,… more
